1 features ? high-performance, low-power 8-bit avr ? enhanced risc architecture C 120 powerful instructions C most single clock cycle execution ? up to 48k bytes flash program memory C endurance: 10,000 write/erase cycles ? up to 48k bytes eeprom user memory C endurance: 100,000 write/erase cycles ? up to 2.5k bytes ram ? cryptoprocessor C pre-programmed functions for cryptography and authentication ? supervisor mode (memory management) ? iso 7816 i/o port ? random number generator ? 16-bit timer ? 2-level, 5-vector interrupt controller ? security features C power-down protection C low-frequency protection C high-frequency filter C logical scrambling on program code ? low-power idle and power-down modes ? bond pad locations conform to iso 7816 ? v cc : 3.0v to 5.0v description the at90sc series is a low-power, high-performance, 8-bit microcontroller with flash program memory and eeprom data memory, based on the avr ? enhanced risc architecture. by executing powerful instructions in a single clock cycle, the at90sc achieves throughputs of 1 mips per mhz. its harvard architecture includes 32 gen- eral-purpose working registers directly connected to the alu, allowing two indepen- dent registers to be accessed in one single instruction executed in one clock cycle. some products in the at90sc family feature a cryptoprocessor: a 16-bit crypto engine dedicated to performing fast encryption or authentication functions (see table below). additional security features include power and frequency protection logic, log- ical scrambling on program data and addresses, and memory accesses controlled by a supervisor mode. the at90sc family provides up to 96k bytes of atmels high-density, nonvolatile memory technology. the on-chip downloadable flash allows the program memory to be reprogrammed in-system. this technology combined with the versatile 8-bit cpu on a monolithic chip provides a highly flexible and cost-effective solution to many smart card applications. table 1. the at90sc family device program memory flash bytes user memory eeprom bytes ram bytes crypto- processor at90sc1616c 16k 16k 1k yes at90sc3232 32k 32k 1.5k no AT90SC3232C 32k 32k 1k yes at90sc3220 32k 20k 1.5k no at90sc248c 24k 8k 1k yes at90sc4848c 48k 48k 2.5k yes rev. 1065bsC04/99 secure microcontrollers for smart cards at90sc summary complete datasheet available under nda
at90sc 2 block diagram note: 1. only available on products featuring a cryptoprocessor. pin description vcc supply voltage. gnd ground. rst reset input. a low level on this pin for two clock cycles while the at90sc is running resets the device. this pin includes an internal pull-up resistor. clk clock input to internal clock operating circuit. this pin includes an internal pull-up resistor. in/out in/out is a single bit open drain bi-directional i/o port. this bi-directional pin includes a pull-up resistor. instruction decoder flash program memory instruction register access control general purpose registers x y z status register rom (1) crypto- processor (1) ram data memory secure control interrupt unit iso 7816 i/o port timer v cc gnd control lines alu eeprom user memory otp pc clk access control in/out data bus 8-bit random number generator 16 16 16 v cc 8 88
at90sc 3 8-bit risc microcontroller cpu: avr the avr uses a harvard architecture concept with sepa- rate memories and buses for program and data. the pro- gram memory is accessed with a two stage pipeline. while one instruction is being executed, the next instruction is prefetched from the program memory. this concept enables instructions to be executed in every clock cycle. the fast-access register file concept contains 32 x 8 gen- eral purpose working registers with a single clock cycle access time. this means that during one single clock cycle, one alu operation is executed. two operands are output from the register file, the operation is executed, and the result is stored back in the register file in one clock cycle. the timer and other i/o functions are located in the i/o memory space. the 64 addresses of the i/o memory space can be accessed directly as i/o registers or as memory space. memory organization the at90sc microcontrollers have the following memory organization, as shown in figures 1 and 2. program memory: ? 16-bit addressable eeprom user memory ? 16-bit addressable flash program memory data memory: ? 8-bit addressable eeprom user memory ? 8-bit addressable sram shared between avr and crypto engine ? 8-bit registers addressable as data memory the eeprom is shared between program memory and data memory, depending on the mode. the portion of eeprom dedicated to each function is flexible and varies according to the application. program memory is read-only in normal operation mode. both flash and eeprom memory locations are directly addressable. the eeprom memory locations follow the flash memory in the program address space. program memory the at90sc microcontroller has separate address spaces for program memory and data memory. up to 48k bytes of flash program memory are available. figure 1 shows the program memory. data memory the at90sc can directly address up to 64k bytes of data memory. the load and store instructions access the whole data memory. the at90sc family also features 96 bytes of register and i/o space and up to 2.5k bytes of sram. the i/o space of the ram can be accessed by direct addressing. the last page of the eeprom user memory is an otp memory. figure 1. the at90sc program memory figure 2. the at90sc data memory eeprom user memory supervisor protected area program memory interrupt vectors flash eeprom sram shared with crypto otp 64 i/o at direct access 32 general purpose registers i/o registers registers user memory
at90sc 4 flash program memory ? page size of 64 bytes ? minimum endurance of 10,000 write/erase cycles ? data retention for a minimum of 10 years the at90sc contains up to 48k bytes of downloadable flash memory for program storage. since all instructions are 16-bit words, the flash is organized as 16k x 16. the flash memory is read-only except during the program download mode. this mode is selected by setting a bit in the memory control i/o register. once the flash memory is loaded, a security feature dis- ables the download function, making the writing of the flash impossible. eeprom user memory ? erasure and writing: - byte-by-byte - bit mode - page mode (64 bytes per page) ? minimum endurance of 100,000 write/erase cycles ? data retention for a minimum of 10 years the user memory is organized as up to 24k x 16. a write mode bit in the memory control register selects byte by byte or page mode. during the write cycle, a bit is set in the memory control register, disabling pending write opera- tions. when the write cycle is finished, this bit is cleared and an interrupt request is generated. in addition, the at90sc features a pseudo bit mode which allows individual bits to be overwritten (one to zero). otp memory the 64 bytes of otp (one-time programmable) memory are found at the top of the eeprom address space. cryptoprocessor the cryptoprocessor is a 16-bit crypto engine dedicated to performing fast encryption or authentication functions. it is based on a parallel risc architecture allowing most instructions to be performed in a single clock cycle. the crypto engine can run in parallel with the microcontroller. an internal 16 x 16 multiplier provides 32-bit results within one cycle. the cryptoprocessor runs on its own internal clock. the rom stores the program code which contains the fol- lowing catalog of functions: ? reset and self test ? random number generation ? exponentiation with crt (241 to 1024) ? exponentiation without crt (241 to 1024) note: new algorithms such as dsa and elliptic curves are under development. ram memory sharing the cryptoprocessor and the avr share the ram memory as follows: when the cryptoprocessor is inactive, the entire ram is accessed by the cpu. when the cryptoprocessor is active, it accesses 768 bytes of ram and the cpu accesses the remaining ram space. operational modes the at90sc features two operational modes: ?a supervisor mode with a privileged access to data, active when code is executed from flash memory ?a user mode with data access restrictions, active when code is executed from eeprom user memory in user mode, direct read and write access to i/o registers and eeprom is not allowed. furthermore, a programma- ble zone in the ram can be reserved for supervisor mode. any attempt to access the i/o, eeprom or reserved ram area generates a maskable interrupt. also, any jump to the supervisor zone in user mode gener- ates a non-maskable security interrupt. the at90sc pro- vides a supervisor call instruction to branch at a defined vector address of the supervisor zone. this powerful hardware solution is specially designed to ensure full separation between applications. it provides secure protection against program dumping and secure data access control.
at90sc 5 security features for security reasons the following list is not exhaustive. ? shipping and initialization are protected by a transport code ? power-down/up protection ? low-frequency protection against static analysis ? high-frequency filter against intrusion ? unique serial number ? supervisor mode ? secured test structure ? logical scrambling ? secure layout iso 7816 i/o port the iso 7816 i/o pin is controlled by the cpu. a low level or a negative edge detected on this pin generates an inter- rupt. interrupt controller the at90sc has a total of five interrupt vectors: security, i/o pin, timer, eeprom end of write cycle and a cryptopro- cessor interrupt. each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in the interrupt mask register located in the i/o memory space. this register also contains a global disable bit which disables all inter- rupts at once. one priority level can be programmed in the interrupt prior- ity register. a second priority level is given by the vector number. the interrupt controller is able to memorize interrupts. it sends them to the microcontroller in the correct order according to their priority level. reduced power mode to exploit the power savings for smart cards available in cmos circuitry, atmels microcontrollers have two soft- ware-invoked reduced power modes. idle mode during idle mode, the cpu is disabled while all on-chip peripherals (ram, i/o registers, timer and serial port) remain active. this mode is invoked by a sleep instruc- tion and by an enabled bit in an i/o register. idle mode can be terminated by any enabled interrupt or by a hardware reset. if a reset occurs during sleep mode, the cpu awakes and executes from the reset vector. if an interrupt occurs, the cpu awakes and executes the interrupt routine, and resumes execution from the instruc- tion following sleep. power-down mode during power-down mode, the clock is frozen. the on-chip ram and i/o registers retain their values until power-down mode is terminated. the sleep instruction forces this mode. exit from power-down can be initiated either by a hardware reset or by the enabled external interrupt. reset redefines the i/o registers but does not change the on-chip ram. the i/o registers keep their value if the exit from power-down is generated by an external interrupt. download mode the at90sc microcontroller has a special mode which allows the flash to be written for new software download. the new software is loaded through the iso port and writ- ten into the flash memory. this download mode is soft- ware controlled, so if the software in use does not contain the download facility, no new program can be loaded. if the product contains only flash for the code, during program download (os or application) the code is fetched from the eeprom. timer the at90sc provides a 16-bit general timer with prescaler. the timer can run on a 16-bit counter or on an 8-bit counter with auto-reload mode. the two different prescaler selec- tions are clk or clk/32.
at90sc 6 the instruction set all members of the at90sc series execute the same instruction set. the 16-bit instruction set provides a variety of fast addressing modes to facilitate byte and word opera- tions on small data structures. the instruction set supports 32 general-purpose registers. addressing mode the at90sc avr risc microcontroller supports powerful and efficient addressing modes for access to program and data memory: ? direct i/o addressing ? direct register addressing with one or two registers ? data direct : operand address is specified by a 16-bit code ? indirect address data: operand address is a 16-bit register ? indirect data with displacement : operand address is a 16-bit register with a 6-bit offset ? indirect data with pre-decrement and post-increment: operand address is a 16-bit register ? access to program memory : operand address is a 16-bit register for access in byte lpm instruction ? indirect program addressing : operand address is a 16-bit register for ijmp and icall ? relative program addressing : operand address is a 16-bit pc with an offset of -2048 to +2047 ? direct program addressing instruction type ? data transfers - from/to internal i/o, ram, registers - from/to internal eeprom - from flash ? arithmetic and logical instruction - manipulation, one or two registers - manipulation, constant and register ? boolean instruction - manipulation and test on bit ? branch instruction - relative branch - indirect branch - conditional skip - unconditional branch - conditional branch - subroutine call and return - interrupt return master clock generation the master clock of the cpu is generated by the external iso 7816 clock.
at90sc 7 dc/ac characteristics notes: 1. a 200k ohm pull-up resistor has been added to all the input ports. 2. a schmitt trigger has been added to all the input ports to improve noise immunity. example of some cryptographic function speeds: 512-bit decoder with crt 60 ms 1024-bit decoder with crt 210 ms symbol parameter condition min typ max units v cc supply voltage 2.7 5.5 v f osc clock input frequency 0.5 6 mhz t cyc cpu cycle time 1/f osc ns v ih input high voltage, inout, clk, rst i ih = 50 m a2.0 v cc + 0.3 v v il input low voltage, inout, clk, rst i il = -50 m a-0.3 0.8 v v oh output high voltage inout i oh = -1 ma 2.4 v cc + 0.3 v i oh = -50 m av cc - 0.5 v cc + 0.3 v v ol output low voltage inout i ol = 2 ma -0.3 0.45 v i ol = 500 m a-0.3 0.3 t r output rise time v cc = 3.3 10 m s v cc = 3.3 rpu = 10k w 1 m s t f output fall time v cc = 3.3 20 ns
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